PCIe Gen6 & 7: Feeding the AI Accelerator
The move from NRZ to PAM4 on the PCIe bus
While NVLink handles GPU-to-GPU traffic, PCIe remains the ultimate bridge for feeding the beast. From NICs (InfiniBand/Ethernet) to NVMe storage and host CPUs, the Peripheral Component Interconnect Express (PCIe) bus is under immense pressure. PCIe Gen6 marks the most significant architectural shift in the standard's history, adopting PAM4 signaling to reach 121 GB/s on an x16 slot.
The PAM4 Revolution
For generations, PCIe used **NRZ (Non-Return-to-Zero)** signaling, effectively transmitting one bit per clock cycle. To double the bandwidth for Gen6, the SIG (Special Interest Group) moved to **PAM4 (Pulse Amplitude Modulation 4-level)**. This encodes two bits per clock cycle by using four voltage levels instead of two.
Performance Scaling Table
| Generation | Signaling | x16 BW (Unidir) | Aggregate BW |
|---|---|---|---|
| PCIe 4.0 | NRZ | 32 GB/s | 64 GB/s |
| PCIe 5.0 | NRZ | 64 GB/s | 128 GB/s |
| PCIe 6.0 | PAM4 | 128 GB/s | 256 GB/s |
| PCIe 7.0 (Spec) | PAM4 | 256 GB/s | 512 GB/s |
Why AI Accelerators Need Gen6/7
- 800G Networking: An 800G NIC (like NVIDIA ConnectX-7/8) saturates a PCIe Gen5 x16 slot. To move toward 1.6T networking, PCIe Gen6 is a hard requirement.
- CXL (Compute Express Link): CXL 3.0/3.1 sits on top of the PCIe Gen6 physical layer. For disaggregated memory (sharing RAM between multiple nodes), the Gen6 bandwidth is critical to keep latencies within acceptable bounds.
- DirectStorage & GDS: Loading terabytes of weights from NVMe drives to GPU VRAM is currently throttled by the PCIe root complex. Doubling PCIe speed directly halves model loading and checkpointing times.
Strategic Recommendation
For 2026/2027 deployments, focus on **PCIe Gen6 readiness**. While PCIe Gen5 is sufficient for current H100/A100 clusters, the next generation of Blackwell and Falcon accelerators will require the Gen6 head-end to feed the 1.6T NICs effectively.