The Layer 1 Physical Barrier

The physical layer is not merely a collection of cables; it is a manifestation of **Maxwell’s Equations**. Whether traveling as an electron displacement current in copper or as an electromagnetic wavetrain in silica glass, data is subject to the immutable laws of electrodynamics. At the speeds required by AI infrastructure (800G and beyond), we no longer treat wires as simple conductors, but as **Waveguides**.

In copper, the **Dielectric Constant** of the insulation and the **Skin Depth** of the conductor determine the velocity of propagation and the frequency-dependent loss. In fiber, the refractive index profile of the core creates a potential well that "traps" light via **Total Internal Reflection**, but even this perfect cage is subject to Rayleigh scattering—photons colliding with atomic-scale density fluctuations in the glass.

As we hit the bandwidth limits of simple **NRZ (Non-Return to Zero)** encoding, the industry transitioned to **PAM4 (Pulse Amplitude Modulation 4-Level)**. Instead of a simple "On/Off" state, PAM4 uses four distinct voltage levels to represent two bits per clock cycle.

The physical cost of PAM4 is severe: because the four voltage levels are squeezed into the same total power envelope, the "eyes" (the gap between levels) are significantly smaller. This makes the signal extremely vulnerable to the **Thermal Noise Floor** and necessitates the use of heavy **Forward Error Correction (FEC)** to clean up the inevitable errors.

In the era of Terabit switching, the most significant physical layer constraint is no longer attenuation—it is **The Thermal Wall**. Every time we charge and discharge the parasitic capacitance of a copper trace, or drive a laser diode in an optical module, we consume energy.

This is measured in **picojoules per bit (pJ/bit)**. For 800G Pluggable optics, the energy consumption is approximately **20-25 pJ/bit**. If we want to reach 3.2T and beyond, we must reduce this to below **5 pJ/bit**. This physical reality is the primary driver behind **Co-Packaged Optics (CPO)** and **Silicon Photonics**, where we move the optical interface closer to the ASIC to eliminate the power-hungry copper SerDes links.

To visualize the health of the physical layer, engineers use the **Eye Diagram**. By overlaying thousands of signal transitions, we create a visual representation of **Jitter**, **Crosstalk**, and **Inter-Symbol Interference (ISI)**. A "Closed Eye" means the noise and timing instability are so high that the receiver can no longer distinguish between a '1' and a '0'.

In standard glass fiber, light travels approximately **31% slower** than it does in a vacuum ($n \approx 1.46$). For high-frequency trading (HFT) and ultra-low latency AI clusters, this delay is unacceptable. **Hollow Core Fiber (HCF)** uses a microstructured photonic bandgap to guide light through an air-filled core ($n \approx 1$).

This physical shift reduces propagation delay from **~5.0 $\mu s/km$** down to **~3.3 $\mu s/km$**. Additionally, because the light does not travel through glass, non-linear effects (like FWM and SPM) are virtually eliminated, allowing for significantly higher launch powers and improved OSNR.

At 400G and 800G, the physical signal is so degraded that the raw (pre-FEC) bit error rate is often as high as $10^{-2}$. Without correction, the link would be unusable. Modern Ethernet uses **KP4 FEC (Reed-Solomon 544, 514)**.

This algorithm adds 30 redundant symbols for every 514 symbols of data, allowing the receiver to mathematically "repair" up to 15 symbol errors per block. This physical-to-logical transformation provides an "Effective Gain" that makes PAM4 transmission across lossy backplanes possible. However, this comes at the cost of **Serialization Latency** (approx. 100-200ns), which becomes a critical bottleneck in distributed GPU training.

The physical layer is vulnerable precisely because it is physical. A fiber "tap" can be achieved by simply bending the fiber beyond its critical radius, allowing a small amount of light to "leak" out via **Evanescent Wave Coupling**.

Advanced network monitoring tools use **Coherent Detection** to monitor the **State of Polarization (SoP)**. Any physical disturbance—like a micro-bend from a tap—will cause a sudden rotation in the signal's polarization. By monitoring the SoP at MHz frequencies, security teams can detect physical intrusions in real-time, often before the data is successfully exfiltrated.

The physical layer doesn't just exist between racks; it exists inside the ASIC. As we shrink SerDes and PHY transistors to the **2nm node**, we encounter the limit of electron confinement. **Quantum Tunnelling**—where electrons "teleport" through supposedly impenetrable insulator barriers—becomes a dominant source of leakage current and noise.

This physical noise floor inside the silicon creates a hard limit on the minimum voltage ($V_{min}$) required to maintain signal integrity, directly contradicting our need to lower power consumption ($P \propto V^2$). Solving this requires **GAA (Gate-All-Around)** transistor architectures, where the physical layer of the transistor is redesigned to provide 4-sided electrostatic control.

To understand why copper fails at 100GHz, we must calculate the depth at which the current density falls to $1/e$ of its surface value:

For copper at 10 GHz, $\delta$ is a mere **0.66 microns**. By the time we reach 112G or 224G signaling, the current is squeezed into such a thin surface layer that the **surface roughness** of the copper foil becomes a major contributor to attenuation. High-performance PCBs for the physical layer must use **Ultra-Low Profile (ULP)** copper to prevent electrons from literally "getting lost" in the jagged peaks and valleys of the conductor wall.

As of 2026, the state-of-the-art for the physical layer is **200G per Lambda** (wavelength). Achieving this requires a baud rate of **112 Gbaud** using PAM4. At these speeds, the "baud interval" (the time for one symbol) is less than **9 picoseconds**.

Light travels only **2.7 millimeters** in one symbol period. This physical constraint means that even a 1mm difference in trace length between the laser and the modulator results in catastrophic **Skew**. Data center switches now utilize **Automated Skew Compensation**—using onboard DSPs to delay signal lanes at the femtosecond level to reconcile the physical realities of manufacturing tolerances with the high-speed requirements of the 200G physical layer.