Rack Infrastructure Engine
Configure cluster density and cooling metrics to analyze total facility power draw and thermal impact.
Rack Configuration
Infrastructure
Rack Power Summary
Total rack power draw including IT equipment and cooling (PUE factor).
Current draw per phase on a 208V 3-phase circuit. Standard for North American data centers.
Tons of refrigeration needed to dissipate rack heat. 1 ton ≈ 12,000 BTU/hr.
Total facility power attributed to each GPU, including switches, PDUs, and cooling overhead.
Power Breakdown
IT Equipment
IT Equipment
Total power drawn by all GPUs at TDP.
Total power drawn by all network switches.
Power distribution unit losses (100W per PDU typical).
Sum of all IT equipment power before cooling overhead.
With PUE 1.4
Facility Power
Total facility power including cooling overhead.
Heat output in British Thermal Units per hour.
Refrigeration capacity required to dissipate heat.
Percentage of total power consumed by GPUs (vs switches + PDUs + cooling).
Annual Operating Costs
Annual Operating Costs
Total kilowatt-hours consumed annually by the rack.
Estimated annual electricity cost at $0.10/kWh.
Current draw at 208V 3-phase. Standard North American rack power.
Current draw at 480V 3-phase. Higher voltage reduces line losses.
Engineering Insight
Network switches add ~10-15% overhead to GPU power. Factor PUE of 1.4 into total facility planning. Annual cost: $8,339.52 at $0.10/kWh.
1. 3-Phase Phase Forensics: The Neutral Potential Risk
In high-density GPU racks, power is delivered via 3-phase circuits. If the IT load is not distributed evenly across Phase A, B, and C, it creates an imbalance that forces current into the neutral conductor.
Neutral Current Calculation
The Logic Jitter Hazard: In Wye configurations, excessive neutral current creates a 'Neutral-to-Ground' voltage potential. Voltages exceeding can interfere with the signaling of sensitive GPU memory controllers, leading to 'Silent Data Errors' (SDE) that corrupt training weights.
2. The 415V Pivot: Eliminating Resistive Waste
Heat generated in power cables () represents pure energy waste. By moving from legacy to , we drastically improve power integrity.
75% Loss Reduction
Because resistive loss is proportional to the square of current, doubling the voltage reduces the current by 50% and the heat loss by 75%.
Copper Efficiency
Reducing current allows for thinner, more flexible PDU whip cables, which improves airflow in the rear of the rack—a critical factor for air-cooled servers.
3. GPU Step-Loads: The di/dt Kinetic
AI training workloads are not 'Steady State.' Large Language Models (LLMs) training involves synchronized 'Epochs' where thousands of GPUs jump from idle to peak power in milliseconds.
Even microscopic inductance ($L$) in the power bus creates massive voltage spikes ($\Delta V$) when current ($i$) changes instantly ($dt$). This is why AI power chains require massive local capacitance and ultra-fast UPS bypass logic.
4. The Liquid Era: GPM vs. CFM Capacity
Air (CFM) has reached its physical limit. At per rack, the velocity of air required to move that much heat creates noise levels that exceed OSHA safety limits and creates pressure differentials that can trigger fire suppression sensors.
Liquid (GPM)
Water is x more thermally conductive than air. A standard pipe can move more heat as liquid than a fan can move as air. Required flow: .
Air (CFM)
Limited by the 'Delta T' (temperature difference). To cool $40$kW with air requires $\approx 6,000$ CFM—enough air to physically lift a human if focused through a small vent.
5. Redundancy Forensics: ATS vs. STS
How fast can you switch power when a PDU fails? In AI networking, anything slower than a quarter-cycle () is too slow.
Switching Time Logic
ATS (Mechanical) takes . While servers have capacitors to bridge this gap, AI 'Spine' switches often reset, causing a cluster-wide InfiniBand re-fabrication that kills the training job. STS (Solid-State) is mandatory for the fabric layer.
Frequently Asked Questions
Technical Standards & References
Related Engineering Resources
3-Phase Power Balancing for GPU Racks
GPU racks draw extremely high per-phase currents that must be carefully balanced across A, B, and C phases. A phase imbalance of more than 20% can cause neutral conductor overheating, transformer derating, and nuisance breaker trips at the PDU.
Phase Imbalance and Neutral Current
In a balanced 3-phase system, the neutral current is zero. With imbalance, the neutral carries the vector sum of the phase currents: (with 120-degree phase separation). For a 40 kW rack with 8x H100 GPUs, each drawing plus switch overhead (), the total is approximately . At 208V, the per-phase current is if perfectly balanced.
Dynamic Load Shedding Strategies
AI training power draw fluctuates with GPU utilization. During gradient accumulation, GPUs draw near-idle power (), but during backpropagation, they spike to . These load changes happen on sub-second timescales, requiring dynamic phase balancing. Software-defined PDUs can reassign outlet-to-phase mapping based on real-time current monitoring. The optimal reassignment period is — fast enough to track training phases but slow enough to avoid relay wear.
Transient Voltage Margins During GPU Step-Load Events and PDU Response Times
GPU clusters exhibit extreme power draw transients when training jobs start or checkpoint, transitioning from near-idle (50-100 W per GPU) to full-load (700-1,000 W per GPU) within microseconds. For an NVIDIA H100 SXM5 GPU, the di/dt (current change per unit time) during a transition from idle to active computation reaches 200-400 A/μs per GPU at 0.8 V core voltage. Aggregated across 8 GPUs in a DGX H100 node, the node-level di/dt is 1,600-3,200 A/μs. This translates to a voltage drop at the PDU output of ΔV = L_total × di/dt, where L_total is the combined inductance of the PDU whip cable, the rack busbar, and the node power cable. For a typical 3-meter 6 AWG whip cable with 0.35 μH/m inductance, a 0.5-meter rack busbar with 0.25 μH/m, and a 2-meter C19 power cord with 0.4 μH/m, the total inductance is L_total = 3 × 0.35 + 0.5 × 0.25 + 2 × 0.4 = 1.05 + 0.125 + 0.8 = 1.975 μH. A 2,000 A/μs step-load produces ΔV = 1.975 × 2,000 = 3,950 V/μs, which is not a sustained drop but rather a transient voltage sag that lasts for the duration of the PDU's response time. The PDU's output capacitor bank must supply the instantaneous current until the PDU's voltage regulator loop responds, typically within 10-100 μs. During this response window, the output voltage can sag below the GPU power supply's undervoltage lockout (UVLO) threshold, causing the GPUs to reset or the entire node to power-cycle.
The PDU output capacitor bank sizing determines the maximum voltage sag during the step-load event. The required output capacitance to keep the voltage sag below the UVLO threshold (typically -5% of nominal for GPU power supplies) is C_out = (I_step × T_response) / (V_nom × ΔV_max_percent). For a 45 kW rack with 8 DGX H100 nodes, I_step = 45,000 W / 208 V = 216 A per phase. With T_response = 50 μs, V_nom = 208 V, and ΔV_max_percent = 5% = 10.4 V, C_out = (216 × 50 × 10⁻⁶) / 10.4 = 10,800 / 10.4 = 1,038 μF. This must be distributed across the PDU's three output phases. If the PDU has only 500 μF per phase, the voltage sag reaches ΔV = (216 × 50 × 10⁻⁶) / 500 × 10⁻⁶ = 10,800 / 500 = 21.6 V, or 10.4% of nominal—exceeding the UVLO threshold and causing the node-level power supplies to drop out. The countermeasure is either: (1) increasing the PDU output capacitance to at least 1,000 μF per phase, (2) reducing the PDU response time by using a faster voltage regulator (e.g., moving from a 100 μs response linear regulator to a 10 μs response switching regulator), or (3) implementing a current slew-rate limiter at the GPU node that caps di/dt to 100 A/μs by staging the GPU boot sequence across the 8 GPUs.
The PPB (Per-Phase Breaker) coordination with GPU step-load transients introduces another failure mode: nuisance tripping of the PDU branch circuit breakers. Standard thermal-magnetic breakers have a trip response that depends on both the magnitude and duration of the overcurrent. A GPU step-load that draws 150% of the breaker rating for 100 μs is well within the breaker's "no-trip" zone (thermal-magnetic breakers are designed to tolerate 10× rated current for 10 ms before the magnetic trip mechanism engages). However, when multiple training jobs start simultaneously across the facility, the cumulative effect of thousands of GPU step-loads creating sub-millisecond current spikes can heat the breaker's bimetal strip enough to cause a delayed trip minutes or hours later—a phenomenon known as cumulative thermal memory. Our rack power model includes a breaker thermal simulation that accumulates the I²t energy from each step-load event and compares it against the breaker's trip curve, alerting the operator when the cumulative energy approaches 80% of the trip threshold. This enables the facility team to schedule job start times to avoid thermal-breaker coordination violations.
The voltage sag propagation through the facility's power distribution hierarchy is a final consideration. The PDU's sag propagates upstream to the step-down transformer, which has its own impedance and response time. A 45 kW PDU sag of 10.4 V causes a reflected sag at the 480 V transformer secondary of ΔV_secondary = ΔV_PDU × (N_secondary / N_primary) = 10.4 × (480 / 208) = 24 V, or 5% of the 480 V secondary voltage. If multiple PDUs in the same transformer zone experience simultaneous step-loads, the aggregate sag on the 480 V bus can reach 10-15%, which is sufficient to cause the upstream UPS inverter to trip on undervoltage (typical threshold is 12% below nominal). Our model dynamically computes the cumulative voltage sag as a function of the number of PDUs in the transformer zone, the step-load duty cycle, and the transformer's per-unit impedance (Z_pu typically 5-7% for 2,500 kVA transformers). This enables the operator to design a power distribution topology that isolates GPU-training PDUs from critical-load PDUs (networking, storage) at the transformer level, preventing GPU-induced sags from taking down the cluster's InfiniBand fabric.
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